Sciweavers

240 search results - page 15 / 48
» vlsi 2005
Sort
View
ISCAS
2005
IEEE
132views Hardware» more  ISCAS 2005»
14 years 1 months ago
A high performance distributed-parallel-processor architecture for 3D IIR digital filters
—Real-time spatio-temporal VLSI 3D IIR digital filters may be used for imaging or beamforming applications employing 3D input signals from synchronously-sampled multi-sensor arra...
Arjuna Madanayake, Leonard T. Bruton
ISCAS
2005
IEEE
127views Hardware» more  ISCAS 2005»
14 years 1 months ago
Convergent micro-pipelines: a versatile operator for mixed asynchronous-synchronous computations
Abstract— Micro-pipelines are linear (1-D) structures for asynchronous communications. In retinotopic VLSI vision chips, communicating over 2-D image regions is a key to efficie...
Valentin Gies, Thierry M. Bernard, Alain Mé...
ASPDAC
2005
ACM
65views Hardware» more  ASPDAC 2005»
14 years 1 months ago
Library cell layout with Alt-PSM compliance and composability
The sustained miniaturization of VLSI feature size presents great challenges to sub-wavelength photolithography and requests usage of many Resolution Enhancement Techniques (RET)....
Ke Cao, Puneet Dhawan, Jiang Hu
VLSID
2005
IEEE
223views VLSI» more  VLSID 2005»
14 years 8 months ago
A New CMOS Current Conveyors Based Translinear Loop for Log-Domain Circuit Design
A novel topology for Translinear (TL) loops comprising of CMOS Second Generation Current Conveyors (CC-II) and diodes is proposed. The proposed methodology opens a new paradigm to...
Debashis Dutta, Wouter A. Serdijn, Swapna Banerjee...
VLSID
2005
IEEE
117views VLSI» more  VLSID 2005»
14 years 8 months ago
On-Chip Voltage Regulator with Improved Transient Response
A new technique has been proposed to improve the transient behavior of the on-chip/embedded voltage regulator. It is realized by introducing a dynamic leakage path at the driver s...
Ashis Maity, R. G. Raghavendra, Pradip Mandal