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VLSID
2005
IEEE
153views VLSI» more  VLSID 2005»
14 years 8 months ago
Electromigration-Aware Physical Design of Integrated Circuits
The electromigration effect within current-density-stressed signal and power lines is an ubiquitous and increasingly important reliability and design problem in sub-micron IC desi...
Göran Jerke, Jens Lienig
FCCM
2005
IEEE
111views VLSI» more  FCCM 2005»
14 years 1 months ago
A High-Performance Asynchronous FPGA: Test Results
We report test results from a prototype asynchronous FPGA (AFPGA) implemented in TSMC’s 0.18μm CMOS process. The AFPGA uses SRAM-based configuration bits with pipelined logic ...
David Fang, John Teifel, Rajit Manohar
ISVLSI
2005
IEEE
80views VLSI» more  ISVLSI 2005»
14 years 1 months ago
Sensitivity Analysis of a Cluster-Based Interconnect Model for FPGAs
Mesh interconnect can be efficiently utilized while tree networks encourage the short routing distances. In this paper, we present the property analysis of a cluster-based interc...
Renqiu Huang, Ranga Vemuri
SBCCI
2005
ACM
136views VLSI» more  SBCCI 2005»
14 years 1 months ago
Current mask generation: a transistor level security against DPA attacks
The physical implementation of cryptographic algorithms may leak to some attacker security information by the side channel data, as power consumption, timing, temperature or elect...
Daniel Mesquita, Jean-Denis Techer, Lionel Torres,...
DFT
2005
IEEE
110views VLSI» more  DFT 2005»
14 years 1 months ago
A design flow for protecting FPGA-based systems against single event upsets
SRAM-based Field Programmable Gate Arrays (FPGAs) are very susceptible to Single Event Upsets (SEUs) that may have dramatic effects on the circuits they implement. In this paper w...
Luca Sterpone, Massimo Violante