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VLSI
2010
Springer
13 years 5 months ago
Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs
—This paper proposes a novel technique to exploit the high bandwidth offered by through silicon vias (TSVs). In the proposed approach, synchronous parallel 3D links are replaced ...
Fengda Sun, Alessandro Cevrero, Panagiotis Athanas...
VLSI
2010
Springer
13 years 5 months ago
Trends and techniques for energy efficient architectures
Abstract--Microprocessor architectures have become increasingly power limited in recent years. Currently power and thermal envelopes dictate peak performance limits more than any o...
Victor Jimenez, Roberto Gioiosa, Eren Kursun, Fran...
VLSI
2010
Springer
13 years 2 months ago
Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs
A novel Capacitor array structure for Successive Approximation Register (SAR) ADC is proposed. This circuit efficiently utilizes charge recycling to achieve high-speed of operation...
Yan Zhu, U. Fat Chio, He Gong Wei, Sai-Weng Sin, S...
GLVLSI
2010
IEEE
119views VLSI» more  GLVLSI 2010»
14 years 16 days ago
Line width optimization for interdigitated power/ground networks
Higher operating frequencies have increased the importance of inductance in power and ground networks. The effective inductance of the power and ground network can be reduced with...
Renatas Jakushokas, Eby G. Friedman
GLVLSI
2010
IEEE
154views VLSI» more  GLVLSI 2010»
13 years 9 months ago
Resource-constrained timing-driven link insertion for critical delay reduction
For timing-driven or yield-driven designs, non-tree routing has become more and more popular and additional loops provide the redundant paths to protect against the effect of the ...
Jin-Tai Yan, Zhi-Wei Chen