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VLSID
2003
IEEE
103views VLSI» more  VLSID 2003»
14 years 9 months ago
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program
In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number ofconstraints. By intr...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...
VLSID
2003
IEEE
167views VLSI» more  VLSID 2003»
14 years 9 months ago
Timing Minimization by Statistical Timing hMetis-based Partitioning
In this paper we present statistical timing driven hMetisbased partitioning. We approach timing driven partitioning from a different perspective: we use the statistical timing cri...
Cristinel Ababei, Kia Bazargan
VLSID
2003
IEEE
82views VLSI» more  VLSID 2003»
14 years 9 months ago
SPaRe: Selective Partial Replication for Concurrent Fault Detection in FSMs
We propose a non-intrusive methodology for concurrent fault detection in FSMs. The proposed method is similar to duplication, wherein a replica of the circuit acts as a predictor ...
Petros Drineas, Yiorgos Makris
VLSID
2003
IEEE
180views VLSI» more  VLSID 2003»
14 years 9 months ago
Automating Formal Modular Verification of Asynchronous Real-Time Embedded Systems
Most verification tools and methodologies such as model checking, equivalence checking, hardware verification, software verification, and hardware-software coverification often fl...
Pao-Ann Hsiung, Shu-Yu Cheng
VLSID
2003
IEEE
92views VLSI» more  VLSID 2003»
14 years 9 months ago
Energy Efficient Scheduling for Datapath Synthesis
In this paper, we describe two new algorithms for datapath scheduling which aim at energy reduction while maintaining performance. The proposed algorithms, time constrained and re...
Saraju P. Mohanty, N. Ranganathan