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VLSID
2007
IEEE
131views VLSI» more  VLSID 2007»
14 years 5 months ago
A Placement Methodology for Robust Clocking
As the VLSI technology scales towards the nanometer regime, circuit performance is increasingly affected by variations. These variations need to be considered at an early stage in...
Ganesh Venkataraman, Jiang Hu
VLSID
2007
IEEE
160views VLSI» more  VLSID 2007»
14 years 11 months ago
Spectral RTL Test Generation for Microprocessors
We introduce a novel method of test generation for microprocessors at the RTL using spectral methods. Test vectors are generated for RTL faults, which are the stuck-at faults on i...
Nitin Yogi, Vishwani D. Agrawal
VLSID
2007
IEEE
91views VLSI» more  VLSID 2007»
14 years 11 months ago
Reusing Learned Information in SAT-based ATPG
The robustness of engines for ATPG has to be improved to cope with the growing size of circuits. Recently, SAT-based ATPG approaches have been shown to be very robust even on larg...
Görschwin Fey, Rolf Drechsler, Tim Warode
VLSID
2007
IEEE
92views VLSI» more  VLSID 2007»
14 years 11 months ago
Floorplanning in Modern FPGAs
State-of-the-art FPGA architectures have millions of gates in CLBs, Block RAMs, and Multiplier blocks which can host fairly large designs. While their physical design calls for oor...
Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu
VLSID
2007
IEEE
120views VLSI» more  VLSID 2007»
14 years 11 months ago
Interframe Bus Encoding Technique for Low Power Video Compression
This paper proposes a data encoder to reduce switched capacitance on system bus. Our method focuses on transferring raw video data (pixels) between off-chip memory and on-chip mem...
Asral Bahari, Tughrul Arslan, Ahmet T. Erdogan