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vts 1995
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VTS
1995
IEEE
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VTS 1995
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Partial scan designs without using a separate scan clock
13 years 11 months ago
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cadlab.ece.ucsb.edu
Kwang-Ting Cheng
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20
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VTS
1995
IEEE
76
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VTS 1995
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Reliability evaluation of combinational logic circuits by symbolic simulation
13 years 11 months ago
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www.sti.uniurb.it
Alessandro Bogliolo, Maurizio Damiani, Piero Olivo...
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VTS
1995
IEEE
114
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A portable ATPG tool for parallel and distributed systems
13 years 11 months ago
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www.cad.polito.it
Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo,...
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VTS
1995
IEEE
80
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VTS 1995
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Improving topological ATPG with symbolic techniques
13 years 11 months ago
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Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda,...
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21
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VTS
1995
IEEE
99
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VTS 1995
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Arithmetic built-in self test for high-level synthesis
13 years 11 months ago
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dit.upc.es
In this paper, we propose an entirely new Built-In Self Test scheme for high-level synthesis of data path architectures that makes use of the arithmetic blocks in the data path to...
Nilanjan Mukherjee, H. Kassab, Janusz Rajski, Jerz...
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