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    Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion
    14 years 20 days ago
    Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion
    Download  cseweb.ucsd.edu
    Starting at the 65-nm node, stress engineering to improve the performance of transistors has been a major industry focus. An intrinsic stress source--shallow trench isolation (STI)...
    Andrew B. Kahng, Puneet Sharma, Rasit Onur Topalog...
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