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TCAD
2008
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TCAD 2008
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Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion
15 years 4 months ago
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cseweb.ucsd.edu
Starting at the 65-nm node, stress engineering to improve the performance of transistors has been a major industry focus. An intrinsic stress source--shallow trench isolation (STI)...
Andrew B. Kahng, Puneet Sharma, Rasit Onur Topalog...
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