Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion

Starting at the 65-nm node, stress engineering to improve the performance of transistors has been a major industry focus. An intrinsic stress source--shallow trench isolation (STI)--has not been fully utilized up to now for circuit performance improvement. In this paper, we present a new methodology that combines detailed placement and active-layer fill insertion to exploit STI stress for performance improvement. We conduct process simulation of a 65-nm production STI technology to generate mobility and delay impact models for STI stress. We then utilize these models to perform STI-stress-aware delay analysis of critical paths using Simulation Program with Integrated Circuit Emphasis (SPICE). We present our timing-driven optimization of STI stress in standard cell designs, using detailed placement perturbation and active-layer fill insertion to improve complementary metal

• Type: Journal
• Year: 2008
• Where: TCAD
• Authors: Andrew B. Kahng, Puneet Sharma, Rasit Onur Topaloglu
• Keywords: 65-nm Production Sti, Clock Frequency, Performance Improvement, TCAD 2008