We present BonnPlace, a new VLSI placement algorithm that combines the advantages of analytical and partitioning-based placers. Based on (non-disjoint) placements minimizing the t...
Layout parasitics have great impact on analog circuit performance. This paper presents an algorithm for explicit parasitic control during layout retargeting of analog integrated c...
In this paper we discuss an efficient design flow from Matlab® to FPGA. Employing Matlab for algorithm research and as system level language allows efficient transition from algo...
We propose a hierarchical mixed signal design methodology based on the principles of Platform-Based Design (PBD). The methodology is a meet-in-the-middle approach where design com...
Fernando De Bernardinis, Pierluigi Nuzzo, Alberto ...
In this paper we present the impact of dynamically translating any sequence of instructions into combinational logic. The proposed approach combines a reconfigurable architecture ...
Spatially distributed 3D circuit models are extracted with a segmentto-segment BEM (Boundary Element Method) algorithm for both capacitance and inverse inductance couplings rather...
Michael W. Beattie, Hui Zheng, Anirudh Devgan, Byr...
This paper presents an efficient hardware architecture of an on-chip logic minimization coprocessor. The proposed architecture employs TCAM cells to provide fastest and memory eï¬...
In this paper, we propose a new sensitivity based, statistical gate sizing method. Since circuit optimization effects the entire shape of the circuit delay distribution, it is dif...
Aseem Agarwal, Kaviraj Chopra, David Blaauw, Vladi...