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Abstract—With delays due to the physical interconnect dominating the overall logic path delays, circuit-level delay optimization must take interconnect effects into account. Inst...
Noel Menezes, Satyamurthy Pullela, Lawrence T. Pil...
To save memory, layout-to-circuit extractors that use the Finite-Element Method for resistance extraction usually solve the corresponding set of equations with a frontal solution ...
A new approa ch for pe r f or ma nc e -dr ive n r outi ng i n hi ghly c onge st e d hi gh s pe e d MCMs a nd PCBs i s pr e s e nt e d. Gl oba l r out i ng i s e mpl oye d t o ma n...
- Power estimation in combinational modules is addressed from a probabilistic point of view. The zero-delay hypothesis is considered and under highly correlated input streams, the ...
Abstract— Many asynchronous designs are naturally specified and implemented hierarchically as an interconnection of separate asynchronous modules that operate concurrently and c...
—We address the problem of code optimization for embedded DSP microprocessors. Such processors (e.g., those in the TMS320 series) have highly irregular datapaths, and conventiona...
Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Stev...