Sciweavers

APCSAC
2003
IEEE
14 years 3 months ago
On Implementing High Level Concurrency in Java
Abstract. Increasingly threading has become an important architectural component of programming languages to support parallel programming. Previously we have proposed an elegant la...
G. Stewart Von Itzstein, Mark Jasiunas
APCSAC
2001
IEEE
14 years 3 months ago
Retargetable Cache Simulation Using High Level Processor Models
During processor design, it is often necessary to evaluate multiple cache configurations. This paper describes the design and implementation of a retargetable on-line cache simula...
Rajiv A. Ravindran, Rajat Moona
APCSAC
2001
IEEE
14 years 3 months ago
The First Real Operating System for Reconfigurable Computers
Traditional reconfigurable computing platforms are designed to be single user and have been acknowledged to be difficult to design applications for. The design tools are still pri...
Grant B. Wigley, David A. Kearney
APCSAC
2001
IEEE
14 years 3 months ago
Exploiting Java Instruction/Thread Level Parallelism with Horizontal Multithreading
Java bytecodes can be executed with the following three methods: a Java interpretor running on a particular machine interprets bytecodes; a Just-In-Time (JIT) compiler translates ...
Kenji Watanabe, Wanming Chu, Yamin Li
APCSAC
2001
IEEE
14 years 3 months ago
Password-Capabilities: Their Evolution from the Password-Capability System into Walnut and Beyond
Since we first devised and defined password-capabilities as a new technique for building capability-based operating systems, a number of research systems around the world have use...
Ronald Pose
APCSAC
2001
IEEE
14 years 3 months ago
Stacking them up: a Comparison of Virtual Machines
A popular trend in current software technology is to gain program portability by compiling programs to an inte form based on an abstract machine definition. Such approaches date b...
K. John Gough
APCSAC
2001
IEEE
14 years 3 months ago
High-Performance Extendable Instruction Set Computing
In this paper, a new architecture called the extendable instruction set computer (EISC) is introduced that addresses the issues of memory size and performance in embedded micropro...
Heui Lee, Paul Becket, Bill Appelbe
APCSAC
2001
IEEE
14 years 3 months ago
The SawMill Framework for Virtual Memory Diversity
We present a framework that allows applications to build and customize VM services on the L4 microkernel. While the L4 microkernel's abstractions are quite powerng these abst...
Mohit Aron, Jochen Liedtke, Kevin Elphinstone, Yoo...
DAC
2006
ACM
14 years 3 months ago
IMPRES: integrated monitoring for processor reliability and security
Security and reliability in processor based systems are concerns requiring adroit solutions. Security is often compromised by code injection attacks, jeopardizing even `trusted so...
Roshan G. Ragel, Sri Parameswaran
DAC
2006
ACM
14 years 3 months ago
Refined statistical static timing analysis through
Statistical static timing analysis (SSTA) has been a popular research topic in recent years. A fundamental issue with applying SSTA in practice today is the lack of reliable and e...
Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir