Sciweavers

ANCS
2007
ACM
14 years 3 months ago
Frame shared memory: line-rate networking on commodity hardware
Network processors provide an economical programmable platform to handle the high throughput and frame rates of modern and next-generation communication systems. However, these pl...
John Giacomoni, John K. Bennett, Antonio Carzaniga...
ANCS
2007
ACM
14 years 3 months ago
Performance scalability of a multi-core web server
Today's large multi-core Internet servers support thousands of concurrent connections or flows. The computation ability of future server platforms will depend on increasing n...
Bryan Veal, Annie Foong
ANCS
2007
ACM
14 years 3 months ago
High-speed detection of unsolicited bulk emails
We propose a Progressive Email Classifier (PEC) for highspeed classification of message patterns that are commonly associated with unsolicited bulk email (UNBE). PEC is designed t...
Sheng-Ya Lin, Cheng-Chung Tan, Jyh-Charn Liu, Mich...
ANCS
2007
ACM
14 years 3 months ago
Optimization of pattern matching algorithm for memory based architecture
Due to the advantages of easy re-configurability and scalability, the memory-based string matching architecture is widely adopted by network intrusion detection systems (NIDS). In...
Cheng-Hung Lin, Yu-Tang Tai, Shih-Chieh Chang
ANCS
2007
ACM
14 years 3 months ago
Frame-aggregated concurrent matching switch
Network operators need high-capacity router architectures that can offer scalability, provide throughput and performance guarantees, and maintain packet ordering. However, previou...
Bill Lin, Isaac Keslassy
ANCS
2007
ACM
14 years 3 months ago
Low-latency scheduling in large switches
Scheduling in large switches is challenging. Arbiters must operate at high rates to keep up with the high switching rates demanded by multi-gigabit-per-second link rates and short...
Wladek Olesinski, Nils Gura, Hans Eberle, Andres M...
ANCS
2007
ACM
14 years 3 months ago
Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture
Network-on-Chip (NoC) architectures provide a scalable solution to the wire delay constraints in deep submicron VLSI designs. Recent research into the optimization of NoC architec...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
ANCS
2007
ACM
14 years 3 months ago
Flow-slice: a novel load-balancing scheme for multi-path switching systems
Lei Shi, Bin Liu, Changhua Sun, Zhengyu Yin, Laxmi...
ANCS
2007
ACM
14 years 3 months ago
Ruler: high-speed packet matching and rewriting on NPUs
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...
Tomas Hruby, Kees van Reeuwijk, Herbert Bos