Sciweavers

SEUS
2010
IEEE
13 years 10 months ago
Crash Recovery in FAST FTL
NAND flash memory is one of the non-volatile memories and has been replacing hard disk in various storage markets from mobile devices, PC/Laptop computers, even to enterprise serv...
Sungup Moon, Sang-Phil Lim, Dong-Joo Park, Sang-Wo...
SEUS
2010
IEEE
13 years 10 months ago
Code Generation for Embedded Java with Ptolemy
Abstract. Code generation from models is the ultimate goal of model-based design. For real-time systems the generated code must be analyzable for the worstcase execution time (WCET...
Martin Schoeberl, Christopher Brooks, Edward A. Le...
SEUS
2010
IEEE
13 years 10 months ago
Time-Predictable Computing
Real-time systems need to be time-predictable in order to prove the timeliness of all their time-critical responses. While this is a well-known fact, recent efforts of the communit...
Raimund Kirner, Peter P. Puschner
SEUS
2010
IEEE
13 years 10 months ago
Reactive Clock Synchronization for Wireless Sensor Networks with Asynchronous Wakeup Scheduling
Most of the existing clock synchronization algorithms for wireless sensor networks can be viewed as proactive clock synchronization since they require nodes to periodically synchro...
Sang Hoon Lee, Yunmook Nah, Lynn Choi
SEUS
2010
IEEE
13 years 10 months ago
Error Detection Rate of MC/DC for a Case Study from the Automotive Domain
Chilenski and Miller [1] claim that the error detection probability of a test set with full modified condition/decision coverage (MC/DC) on the system under test converges to 100%...
Susanne Kandl, Raimund Kirner
SAMOS
2010
Springer
13 years 10 months ago
Accelerating high-level engineering computations by automatic compilation of Geometric Algebra to hardware accelerators
Abstract—Geometric Algebra (GA), a generalization of quaternions, is a very powerful form for intuitively expressing and manipulating complex geometric relationships common to en...
Jens Huthmann, Peter Muller, Florian Stock, Dietma...
SAMOS
2010
Springer
13 years 10 months ago
LV*: A low complexity lazy versioning HTM infrastructure
Anurag Negi, M. M. Waliullah, Per Stenström
SAMOS
2010
Springer
13 years 10 months ago
Cycle-accurate performance modelling in an ultra-fast just-in-time dynamic binary translation instruction set simulator
—Instruction set simulators (ISS) are vital tools for compiler and processor architecture design space exploration and verification. State-of-the-art simulators using just-in-ti...
Igor Böhm, Björn Franke, Nigel P. Topham
SAMOS
2010
Springer
13 years 10 months ago
Identifying communication models in Process Networks derived from Weakly Dynamic Programs
—Process Networks (PNs) is an appealing computation ion helping to specify an application in parallel form and realize it on parallel platforms. The key questions to be answered ...
Dmitry Nadezhkin, Todor Stefanov
SAMOS
2010
Springer
13 years 10 months ago
Programming multi-core architectures using Data-Flow techniques
Abstract—In this paper we present a Multithreaded programming methodology for multi-core systems that utilizes DataFlow concurrency. The programmer augments the program with macr...
Samer Arandi, Paraskevas Evripidou