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15

ASPDAC
2010
ACM

110views Hardware» more ASPDAC 2010»

An alternative polychronous model and synthesis methodology for model-driven embedded software

13 years 9 months ago

An alternative polychronous model and synthesis methodology for model-driven embedded software

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Bijoy A. Jose, Sandeep K. Shukla

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29

ASPDAC
2010
ACM

121views Hardware» more ASPDAC 2010»

Current source modeling in the presence of body bias

13 years 9 months ago

Current source modeling in the presence of body bias

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Saket Gupta, Sachin S. Sapatnekar

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25

ASPDAC
2010
ACM

166views Hardware» more ASPDAC 2010»

-Possibility of ESL-: a software centric system design for multicore SoC in the upstream phase

13 years 9 months ago

-Possibility of ESL-: a software centric system design for multicore SoC in the upstream phase

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Koichiro Yamashita

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23

ASPDAC
2010
ACM

105views Hardware» more ASPDAC 2010»

Physical design techniques for optimizing RTA-induced variations

13 years 9 months ago

Physical design techniques for optimizing RTA-induced variations

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Yaoguang Wei, Jiang Hu, Frank Liu, Sachin S. Sapat...

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23

ASPDAC
2010
ACM

105views Hardware» more ASPDAC 2010»

Simultaneous slack budgeting and retiming for synchronous circuits optimization

13 years 9 months ago

Simultaneous slack budgeting and retiming for synchronous circuits optimization

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Shenghua Liu, Yuchun Ma, Xianlong Hong, Yu Wang

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34

ASPDAC
2010
ACM

183views Hardware» more ASPDAC 2010»

Multi-operand adder synthesis on FPGAs using generalized parallel counters

13 years 9 months ago

Multi-operand adder synthesis on FPGAs using generalized parallel counters

Download qir.kyushu-u.ac.jp

Multi-operand adders, which are also found in parallel multipliers, usually consist of the compression trees which reduce the number of operands per a bit to two, and the carrypro...

Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga

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42

ASPDAC
2010
ACM

143views Hardware» more ASPDAC 2010»

A low latency wormhole router for asynchronous on-chip networks

13 years 9 months ago

A low latency wormhole router for asynchronous on-chip networks

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Asynchronous on-chip networks are power efficient and tolerant to process variation but they are slower than synchronous on-chip networks. A low latency asynchronous wormhole route...

Wei Song, Doug Edwards

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37

ASPDAC
2010
ACM

163views Hardware» more ASPDAC 2010»

A PUF design for secure FPGA-based embedded systems

13 years 9 months ago

A PUF design for secure FPGA-based embedded systems

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The concept of having an integrated circuit (IC) generate its own unique digital signature has broad application in areas such as embedded systems security, and IP/IC counterpiracy...

Jason Helge Anderson

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39

ASPDAC
2010
ACM

144views Hardware» more ASPDAC 2010»

Correlating system test Fmax with structural test Fmax and process monitoring measurements

13 years 9 months ago

Correlating system test Fmax with structural test Fmax and process monitoring measurements

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Janine Chen, Jing Zeng, Li-C. Wang, Michael Mateja

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15

ASPDAC
2010
ACM

142views Hardware» more ASPDAC 2010»

Application-specific 3D Network-on-Chip design using simulated allocation

13 years 9 months ago

Application-specific 3D Network-on-Chip design using simulated allocation

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Pingqiang Zhou, Ping-Hung Yuh, Sachin S. Sapatneka...

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