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ASPDAC
2010
ACM
94views Hardware» more  ASPDAC 2010»
13 years 9 months ago
Technology mapping with crosstalk noise avoidance
Fang-Yu Fan, Hung-Ming Chen, I-Min Liu
ASPDAC
2010
ACM
478views Hardware» more  ASPDAC 2010»
13 years 9 months ago
A unified multi-corner multi-mode static timing analysis engine
Jing-Jia Nian, Shih-Heng Tsai, Chung-Yang (Ric) Hu...
ASPDAC
2010
ACM
120views Hardware» more  ASPDAC 2010»
13 years 9 months ago
Wideband reduced modeling of interconnect circuits by adaptive complex-valued sampling method
In this paper, we propose a new wideband model order reduction method for interconnect circuits by using a novel adaptive sampling and error estimation scheme. We try to address t...
Hai Wang, Sheldon X.-D. Tan, Gengsheng Chen
ASPDAC
2010
ACM
137views Hardware» more  ASPDAC 2010»
13 years 9 months ago
Energy and performance driven circuit design for emerging phase-change memory
Abstract--Phase-Change Random Access Memory (PRAM) has become one of the most promising emerging memory technologies, due to its attractive features such as high density, fast acce...
Dimin Niu, Yibo Chen, Xiangyu Dong, Yuan Xie
ASPDAC
2010
ACM
139views Hardware» more  ASPDAC 2010»
13 years 9 months ago
Fixed-outline thermal-aware 3D floorplanning
In this paper, we present a novel algorithm for 3D floorplanning with fixed outline constraints and a particular emphasis on thermal awareness. A computationally efficient thermal ...
Linfu Xiao, Subarna Sinha, Jingyu Xu, Evangeline F...
ASPDAC
2010
ACM
171views Hardware» more  ASPDAC 2010»
13 years 9 months ago
Gate delay estimation in STA under dynamic power supply noise
Takaaki Okumura, Fumihiro Minami, Kenji Shimazaki,...
ASPDAC
2010
ACM
135views Hardware» more  ASPDAC 2010»
13 years 9 months ago
Statistical timing verification for transparently latched circuits through structural graph traversal
Level-sensitive transparent latches are widely used in high-performance sequential circuit designs. Under process variations, the timing of a transparently latched circuit will ada...
Xingliang Yuan, Jia Wang
ASPDAC
2010
ACM
135views Hardware» more  ASPDAC 2010»
13 years 9 months ago
Efficient power grid integrity analysis using on-the-fly error check and reduction
In this paper, we present a new voltage IR drop analysis approach for large on-chip power delivery networks. The new approach is based on recently proposed sampling based reductio...
Duo Li, Sheldon X.-D. Tan, Ning Mi, Yici Cai
ASPDAC
2010
ACM
155views Hardware» more  ASPDAC 2010»
13 years 9 months ago
Efficient model reduction of interconnects via double gramians approximation
The gramian approximation methods have been proposed recently to overcome the high computing costs of classical balanced truncation based reduction methods. But those methods typi...
Boyuan Yan, Sheldon X.-D. Tan, Gengsheng Chen, Yic...