This paper presents an efficient approach to generate tests for gate delay faults. Unlike other known algorithms which try to generate a 'good' delay test the presented ...
This paper describes a technique which uses the Differential Non Linearity (DNL) test data for fault location and identification of the analog components of a flash ADC. In a flash...
Use of current-mode CMOS circuitsfor implementation of multiple-valued logic (MVL)functions has been considered in a number of recent papers. In this paper, we present an applicat...
A construction principle for natural deduction systems for arbitrary finitely-many-valued first order logics is exhibited. These systems are systematically obtained from sequent...