In this paper we study signal alignment resulting in maximum peak interconnect crosstalk noise. We consider two cases. In the first one we assume that arbitrary arrival times of i...
500+ MHz designs using deep-submicron (DSM) copper interconnects require accurate and efficient modeling of cladding-metals’ frequency-dependent impedance [1]. In this paper, fo...
We propose a gate resizing method for delay and power optimization that is based on statistical static timing analysis. Our method focuses on the component of timing uncertainties...
In this paper, we present an algorithm for delay minimization of interconnect trees by simultaneous buffer insertion/sizing and wire sizing. The algorithm integrates the quadratic...