This paper describes an algorithm for simultaneous gate sizing and fanout optimization along the timing-critical paths in a circuit. First, a continuous-variable delay model that ...
In this paper, we propose a novel fault-oriented test generation methodology for detection and isolation of faults in analog circuits. Given the description of the circuit-underte...
The increasing size of integrated systems combined with deep submicron physical modeling details creates an explosion in RLC interconnect modeling complexity of unmanageable propo...
Michael W. Beattie, Satrajit Gupta, Lawrence T. Pi...
In this paper, we present simulation techniques to estimate the worst-case voltage variation using a RC model for the power distribution network. Pattern independent maximum envel...
Reconfigurable chips are integrated circuits whose internal connections can be programmed by the user to attend a specific application. Field Programmable Gate Arrays (FPGAs) and ...
Ricardo Salem Zebulum, Cristina Costa Santini, Hel...
Evolvable Hardware (EHW) has the potential to become a new target hardware for complex real-world applications. However, there are several problems that would have to be solved to...
Evolvable Hardware (EHW) refers to HW design and selfreconfiguration using evolutionary/genetic mechanisms. The paper presents an overview of some key concepts of EHW, describing ...
Adrian Stoica, Didier Keymeulen, Ricardo Salem Zeb...