ICS
2004
Tsinghua U.
14 years 6 months ago
2004
Tsinghua U.
ICS
2004
Tsinghua U.
14 years 6 months ago
2004
Tsinghua U.
In contemporary out-of-order superscalar design, high IPC is mainly achieved by exposing high instruction level parallelism (ILP). Scaling issue window size can certainly provide ...
ICS
2004
Tsinghua U.
14 years 6 months ago
2004
Tsinghua U.
Studying program behavior is a central component in architectural designs. In this paper, we study and exploit one aspect of program behavior, the behavior repetition, to expedite...
ICS
2004
Tsinghua U.
14 years 6 months ago
2004
Tsinghua U.
ICS
2004
Tsinghua U.
14 years 6 months ago
2004
Tsinghua U.
Cache hierarchies have been traditionally designed for usage by a single application, thread or core. As multi-threaded (MT) and multi-core (CMP) platform architectures emerge and...
ICS
2004
Tsinghua U.
14 years 6 months ago
2004
Tsinghua U.
ICS
2004
Tsinghua U.
14 years 6 months ago
2004
Tsinghua U.
With processor speeds continuing to outpace the memory subsystem, cache missing memory operations continue to become increasingly important to application performance. In response...
ICS
2004
Tsinghua U.
14 years 6 months ago
2004
Tsinghua U.
The Cray X1 was recently introduced as the first in a new line of parallel systems to combine high-bandwidth vector processing with an MPP system architecture. Alongside capabili...
ICS
2004
Tsinghua U.
14 years 6 months ago
2004
Tsinghua U.
Storage mapping optimization is a flexible approach to folding array dimensions in numerical codes. It is designed to reduce the memory footprint after a wide spectrum of loop tr...
ICS
2004
Tsinghua U.
14 years 6 months ago
2004
Tsinghua U.
The growing dominance of wire delays at future technology points renders a microprocessor communication-bound. Clustered microarchitectures allow most dependence chains to execute...