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36

ARVLSI
1995
IEEE

124views VLSI» more ARVLSI 1995»

An evaluation of bipartitioning techniques

14 years 5 months ago

Logic partitioning is an important issue in VLSI CAD, and has been an area of active research for at least the last 25 years. Numerous approaches have been developed and many diff...

Scott Hauck, Gaetano Borriello

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38

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ARVLSI
1995
IEEE

179views VLSI» more ARVLSI 1995»

Algorithms for the optimal state assignment of asynchronous state machines

14 years 5 months ago

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This paper presents a method for the optimal state assignment of asynchronous state machines. Unlike state assignment for synchronous state machines, state codes must be chosen ca...

Robert M. Fuhrer, Bill Lin, Steven M. Nowick

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44

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ARVLSI
1995
IEEE

132views VLSI» more ARVLSI 1995»

Standard CMOS active pixel image sensors for multimedia applications

14 years 5 months ago

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The task of image acquisition is completely dominated by CCD-based sensors fabricated on specialized process lines. These devices provide an essentially passive means of detecting...

Alex G. Dickinson, Bryan D. Ackland, El-Sayed Eid,...

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33

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ARVLSI
1995
IEEE

146views VLSI» more ARVLSI 1995»

Array-of-arrays architecture for parallel floating point multiplication

14 years 5 months ago

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This paper presents a new architecture style for the design of a parallel ﬂoating point multiplier. The proposed architecture is a synergy of trees and arrays. Architectural mod...

H. Dhanesha, K. Falakshahi, Mark Horowitz

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31

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ARVLSI
1995
IEEE

155views VLSI» more ARVLSI 1995»

Low-latency plesiochronous data retiming

14 years 5 months ago

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A new method of retiming plesiochronous data is described. This method features latency of less than a cell-time and requires only minimal support circuitry. No flow control or ha...

Larry R. Dennison, William J. Dally, Thucydides Xa...

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30

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ARVLSI
1995
IEEE

151views VLSI» more ARVLSI 1995»

Silicon VLSI processing architectures incorporating integrated optoelectronic devices

14 years 5 months ago

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Huy Cat, Myunghee Lee, Brent Buchanan, D. Scott Wi...

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48

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ARVLSI
1997
IEEE

151views VLSI» more ARVLSI 1997»

The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors

14 years 5 months ago

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A microprocessor integrated with DRAM on the same die has the potential to improve system performance by reducing the memory latency and improving the memory bandwidth. However, a...

Tadaaki Yamauchi, Lance Hammond, Kunle Olukotun

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38

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ARVLSI
1997
IEEE

138views VLSI» more ARVLSI 1997»

Kestrel: Design of an 8-bit SIMD Parallel Processor

14 years 5 months ago