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ARITH
1999
IEEE
14 years 4 months ago
Floating-Point Unit in Standard Cell Design with 116 Bit Wide Dataflow
The floating-point unit of a S/390 CMOS microprocessor is described. It contains a 116 bit fraction dataflow for addition and subtraction and a 64 bit-wide multiplier. Besides the...
Guenter Gerwig, Michael Kroener
ARITH
1999
IEEE
14 years 4 months ago
Multiplications of Floating Point Expansions
In modern computers, the floating point unit is the part of the processor delivering the highest computing power and getting most attention from the design team. Performance of an...
Marc Daumas
ARITH
1999
IEEE
14 years 4 months ago
Correctness Proofs Outline for Newton-Raphson Based Floating-Point Divide and Square Root Algorithms
This paper describes a study of a class of algorithms for the floating-point divide and square root operations, based on the Newton-Raphson iterative method. The two main goals we...
Marius A. Cornea-Hasegan, Roger A. Golliver, Peter...
ARITH
1999
IEEE
14 years 4 months ago
Complex Logarithmic Number System Arithmetic Using High-Radix Redundant CORDIC Algorithms
This paper describes the application of high radix redundant CORDIC algorithms to complex logarithmic number system arithmetic. It shows that a CLNS addition can be performed with...
David Lewis
ARITH
1999
IEEE
14 years 4 months ago
Necessary and Sufficient Conditions for Parallel, Constant Time Conversion and Addition
This note presents necessary and sufficient conditions for parallel and constant time conversions from one digit-set into another, and thus also for constant time addition. In the...
Peter Kornerup
ARITH
1999
IEEE
14 years 4 months ago
Montgomery Modular Exponentiation on Reconfigurable Hardware
It is widely recognized that security issues will play a crucial role in the majority of future computer and communication systems. Central tools for achieving system security are...
Thomas Blum
ARITH
1999
IEEE
14 years 4 months ago
A Comparison of Three Rounding Algorithms for IEEE Floating-Point Multiplication
A new IEEE compliant floating-point rounding algorithm for computing the rounded product from a carry-save representation of the product is presented. The new rounding algorithm i...
Guy Even, Peter-Michael Seidel
ARITH
1999
IEEE
14 years 4 months ago
Reduced Latency IEEE Floating-Point Standard Adder Architectures
The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses "flagged prefix addition" to merge rounding with the s...
Andrew Beaumont-Smith, Neil Burgess, S. Lefrere, C...
ARITH
1999
IEEE
14 years 4 months ago
On Infinitely Precise Rounding for Division, Square Root, Reciprocal and Square Root Reciprocal
Quotients, reciprocals, square roots and square root reciprocals all have the property that infinitely precise
Cristina Iordache, David W. Matula
ARITH
1999
IEEE
14 years 4 months ago
Interval Sine and Cosine Functions Computation Based on Variable-Precision CORDIC Algorithm
In this paper we design a CORDIC architecture for variable
Javier Hormigo, Julio Villalba, Emilio L. Zapata