Sciweavers

SBRN
2008
IEEE
14 years 6 months ago
Selecting Neural Network Forecasting Models Using the Zoomed-Ranking Approach
In this work, we propose to use the Zoomed-Ranking approach to ranking and selecting Artificial Neural Network (ANN) models for time series forecasting. Given a time series to fo...
Patrícia M. Santos, Teresa Bernarda Ludermi...
SBRN
2008
IEEE
14 years 6 months ago
Combining Distances through an Auto-Encoder Network to Verify Signatures
In this paper we present a system for off-line signature verification. The paper’s contributions are: i) Five distances were calculated and evaluated over the signature databas...
Milena R. P. Souza, Leandro R. Almeida, George D. ...
ISMVL
2008
IEEE
126views Hardware» more  ISMVL 2008»
14 years 6 months ago
Betweenness, Metrics and Entropies in Lattices
We investigate a class of metrics on lattices that are compatible with the partial order defined by the lattice using the ternary relation of betweenness that can be naturally de...
Dan A. Simovici
ISMVL
2008
IEEE
134views Hardware» more  ISMVL 2008»
14 years 6 months ago
Multiple-Valued Logic Memory System Design Using Nanoscale Electrochemical Cells
Nanoscale multiple-valued logic systems require the development of nanometer scale integrated circuits and components. Due to limits in device physics, new components must be deve...
Theodore W. Manikas, Dale Teeters
ISMVL
2008
IEEE
111views Hardware» more  ISMVL 2008»
14 years 6 months ago
Multiple Valued Logic Using 3-State Quantum Dot Gate FETs
Abstract—This paper presents fundamental logic structures designed using novel quantum dot gate FETs with three-state characteristics. This three-state FET manifests itself as a ...
John A. Chandy, Faquir C. Jain
ISMVL
2008
IEEE
119views Hardware» more  ISMVL 2008»
14 years 6 months ago
Encoding Max-CSP into Partial Max-SAT
We define a number of original encodings that map MaxCSP instances into Partial Max-SAT instances. Our encodings rely on the well-known direct and support encodings from CSP into...
Josep Argelich, Alba Cabiscol, Inês Lynce, F...
ISMVL
2008
IEEE
109views Hardware» more  ISMVL 2008»
14 years 6 months ago
Deciding the Satisfiability of Propositional Formulas in Finitely-Valued Signed Logics
Victor Chepoi, Nadia Creignou, Miki Hermann, Gerno...
ISMVL
2008
IEEE
155views Hardware» more  ISMVL 2008»
14 years 6 months ago
Reversible Realization of Quaternary Decoder, Multiplexer, and Demultiplexer Circuits
—A quaternary reversible circuit is more compact than the corresponding binary reversible circuit in terms of number of input/output lines required. Decoder, multiplexer, and dem...
Mozammel H. A. Khan
ISMVL
2008
IEEE
122views Hardware» more  ISMVL 2008»
14 years 6 months ago
RevLib: An Online Resource for Reversible Functions and Reversible Circuits
Synthesis of reversible logic has become an active research area in the last years. But many proposed algorithms are evaluated with a small set of benchmarks only. Furthermore, re...
Robert Wille, Daniel Große, Lisa Teuber, Ger...
ISMVL
2008
IEEE
102views Hardware» more  ISMVL 2008»
14 years 6 months ago
On the Data Structure Metrics of Quantum Multiple-Valued Decision Diagrams
This paper describes new metrics for the data structure referred to as quantum multiple-valued decision diagrams (QMDD) which are used to represent the matrices describing reversi...
David Y. Feinstein, Mitchell A. Thornton, D. Micha...