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ASAP
2009
IEEE
142views Hardware» more  ASAP 2009»
14 years 9 months ago
Parallel Discrete Event Simulation of Molecular Dynamics Through Event-Based Decomposition
—Molecular dynamics simulation based on discrete event simulation (DMD) is emerging as an alternative to time-step driven molecular dynamics (MD). DMD uses simplified discretize...
Martin C. Herbordt, Md. Ashfaquzzaman Khan, Tony D...
ASAP
2009
IEEE
120views Hardware» more  ASAP 2009»
14 years 9 months ago
Design and Implementation of a Radix-4 Complex Division Unit with Prescaling
—We present a design and implementation of a radix-4 complex division unit with prescaling of the operands. Specifically, we extend the treatment of the residual bound and error...
Pouya Dormiani, Milos D. Ercegovac, Jean-Michel Mu...
ASAP
2009
IEEE
115views Hardware» more  ASAP 2009»
14 years 9 months ago
A Novel Processor Architecture for McEliece Cryptosystem and FPGA Platforms
McEliece scheme represents a code-based public-key cryptosystem. So far, this cryptosystem was not employed because of efficiency questions regarding performance and communicatio...
Abdulhadi Shoufan, Thorsten Wink, H. Gregor Molter...
ASAP
2009
IEEE
182views Hardware» more  ASAP 2009»
14 years 9 months ago
NeMo: A Platform for Neural Modelling of Spiking Neurons Using GPUs
—Simulating spiking neural networks is of great interest to scientists wanting to model the functioning of the brain. However, large-scale models are expensive to simulate due to...
Andreas Fidjeland, Etienne B. Roesch, Murray Shana...
ASAP
2009
IEEE
157views Hardware» more  ASAP 2009»
14 years 9 months ago
Low-Power ASIP Architecture Exploration and Optimization for Reed-Solomon Processing
The advent of the mobile age has heavily changed the requirements of today’s communication devices. Data transmission over interference-prone wireless channels requires addition...
Andreas Genser, Christian Bachmann, Christian Steg...
ASAP
2009
IEEE
143views Hardware» more  ASAP 2009»
14 years 9 months ago
Scalar Processing Overhead on SIMD-Only Architectures
—The Cell processor consists of a general-purpose core and eight cores with a complete SIMD instruction set. Although originally designed for multimedia and gaming, it is current...
Arnaldo Azevedo Filho, Ben H. H. Juurlink
ASAP
2009
IEEE
141views Hardware» more  ASAP 2009»
14 years 9 months ago
Accelerating a Virtual Ecology Model with FPGAs
—This paper describes the acceleration of virtual ecology models using field-programmable gate arrays (FPGAs). Our approach targets models generated by the Virtual Ecology Workb...
Julien Lamoureux, Tony Field, Wayne Luk
ASAP
2009
IEEE
144views Hardware» more  ASAP 2009»
14 years 9 months ago
Acceleration of Multiresolution Imaging Algorithms: A Comparative Study
—In this paper we consider a multiresolution filter and its realization on the Cell BE and GPUs. We not only present common and specific optimization strategies undertaken for ...
Richard Membarth, Philipp Kutzer, Hritam Dutta, Fr...