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We study a type of linear placement problem arising in detailed placement optimization of a given cell row in the presence of white-space (extra sites). In this single-row placeme...
Andrew B. Kahng, Paul Tucker, Alexander Zelikovsky
Certain manufacturing steps in very deep submicron VLSI involve chemical-mechanical polishing CMP which has varying e ects on device and interconnect features, depending on loca...
Andrew B. Kahng, Gabriel Robins, Anish Singh, Alex...
: In VLSI circuits with deep sub-micron, the parasitic capacitance from interconnect is a very important factor determining circuit performances such as power and time-delay. The B...