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ISCA
2011
IEEE
229views Hardware» more  ISCA 2011»
13 years 3 months ago
TLSync: support for multiple fast barriers using on-chip transmission lines
As the number of cores on a single-chip grows, scalable barrier synchronization becomes increasingly difficult to implement. In software implementations, such as the tournament ba...
Jungju Oh, Milos Prvulovic, Alenka G. Zajic
MICRO
2010
IEEE
149views Hardware» more  MICRO 2010»
13 years 9 months ago
ReMAP: A Reconfigurable Heterogeneous Multicore Architecture
This paper presents ReMAP, a reconfigurable architecture geared towards accelerating and parallelizing applications within a heterogeneous CMP. In ReMAP, threads share a common rec...
Matthew A. Watkins, David H. Albonesi
IPPS
2010
IEEE
13 years 9 months ago
Inter-block GPU communication via fast barrier synchronization
The graphics processing unit (GPU) has evolved from a fixedfunction processor with programmable stages to a programmable processor with many fixed-function components that deliver...
Shucai Xiao, Wu-chun Feng
IPPS
1997
IEEE
14 years 4 months ago
A Reliable Hardware Barrier Synchronization Scheme
Barrier synchronization is a crucial operation for parallel systems. Many schemes have been proposed in the literature to achieve fast barrier synchronization through software, ha...
Rajeev Sivaram, Craig B. Stunkel, Dhabaleswar K. P...
ICPADS
2005
IEEE
14 years 5 months ago
Efficient Barrier Synchronization on Wireless Computing Systems
This work deals with efficient barrier synchronization for wireless cluster computing where nodes communicate with each other wirelessly in one or multiple hops. Such a computing ...
Nian-Feng Tzeng, Bhanurekha Kasula, Hongyi Wu
IWOMP
2009
Springer
14 years 6 months ago
Scalability Evaluation of Barrier Algorithms for OpenMP
OpenMP relies heavily on barrier synchronization to coordinate the work of threads that are performing the computations in a parallel region. A good implementation of barriers is ...
Ramachandra C. Nanjegowda, Oscar Hernandez, Barbar...