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    PATMOS
    2004
    Springer
    156views Modeling and Simulation» more  PATMOS 2004»
    Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell
    14 years 22 days ago
    Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell
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    A full-adder implemented by combining branch-based logic and pass-gate logic is presented in this contribution. A comparison between this proposed full-adder (named BBL PT) and its...
    Ilham Hassoune, Amaury Nève, Jean-Didier Le...
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