Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell

A full-adder implemented by combining branch-based logic and pass-gate logic is presented in this contribution. A comparison between this proposed full-adder (named BBL PT) and its counterparts in conventional CMOS logic and complementary pass-transistor logic (CPL), was carried out in a 0.13µm PD (partially depleted) SOI CMOS

• Type: Conference
• Year: 2004
• Where: PATMOS
• Authors: Ilham Hassoune, Amaury Nève, Jean-Didier Legat, Denis Flandre
• Keywords: Branch-based Logic, Conventional Cmos Logic, Logic, PATMOS 2004