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ICCD
1997
IEEE
94views Hardware» more  ICCD 1997»
14 years 3 months ago
Pseudo-Random Pattern Testing of Bridging Faults
: This paper studies pseudo-random pattern testing of bridging faults. Although bridging faults are generally more random pattern testable than stuck-at faults, examples are shown ...
Nur A. Touba, Edward J. McCluskey
DATE
2003
IEEE
98views Hardware» more  DATE 2003»
14 years 4 months ago
On the Characterization of Hard-to-Detect Bridging Faults
We investigate a characterization of hard-to-detect bridging faults. For circuits with large numbers of lines (or nodes), this characterization can be used to select target faults...
Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu
DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
14 years 5 months ago
Layout to Logic Defect Analysis for Hierarchical Test Generation
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A...