SC
2009
ACM
14 years 10 months ago
2009
ACM
We present ECC FIFO, a mechanism enabling two-tiered last-level cache error protection using an arbitrarily strong tier-2 code without increasing on-chip storage. Instead of addin...
EUROSYS
2007
ACM
15 years 27 days ago
2007
ACM
The major chip manufacturers have all introduced chip multiprocessing (CMP) and simultaneous multithreading (SMT) technology into their processing units. As a result, even low-end...
HPCA
2007
IEEE
15 years 4 months ago
2007
IEEE
Caches are organized at a line-size granularity to exploit spatial locality. However, when spatial locality is low, many words in the cache line are not used. Unused words occupy ...