ASPLOS
2012
ACM
12 years 8 months ago
2012
ACM
Numerous tools have been proposed to help developers fix software errors and inefficiencies. Widely-used techniques such as memory checking suffer from overheads that limit thei...
CF
2011
ACM
13 years 12 days ago
2011
ACM
Ubiquitous computing has become a very popular paradigm. The most suitable technological solution for those systems consists of using hybrid processors able to operate at high vol...
ISCA
2011
IEEE
13 years 4 months ago
2011
IEEE
Due to shrinking feature sizes processors are becoming more vulnerable to soft errors. Write-back caches are particularly vulnerable since they hold dirty data that do not exist i...
SAC
2008
ACM
13 years 12 months ago
2008
ACM
Leakage power in cache memories represents a sizable fraction of total power consumption, and many techniques have been proposed to reduce it. As a matter of fact, during a fixed ...
ISCA
1999
IEEE
14 years 4 months ago
1999
IEEE
Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it...
CC
2003
Springer
14 years 5 months ago
2003
Springer
Cache memories were invented to decouple fast processors from slow memories. However, this decoupling is only partial, and many researchers have attempted to improve cache use by p...
OTM
2004
Springer
14 years 5 months ago
2004
Springer
Cache memories are mandatory to bridge the growing gap between CPU speed and main memory access time. Standard cache organizations improve the average execution time but are diffi...
ISPASS
2005
IEEE
14 years 6 months ago
2005
IEEE
Cosmic-ray induced soft errors in cache memories are becoming a major threat to the reliability of microprocessor-based systems. In this paper, we present a new method to accurate...
GLVLSI
2008
IEEE
14 years 7 months ago
2008
IEEE
Share of leakage in cache memories is increasing with technology scaling. Studies show that most stored bits in instruction caches are zero, and hence, asymmetric SRAM cells which...