Sciweavers

DSD
2003
IEEE
107views Hardware» more  DSD 2003»
14 years 4 months ago
DYNORA: A New Caching Technique
Cache design for high performance computing requires the realization of two seemingly disjoint goals of higher hit ratios at reduced access times. Recent research advocates the us...
P. Srivatsan, P. B. Sudarshan, P. P. Bhaskaran
HPCA
2002
IEEE
14 years 12 months ago
Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay
Cache memories account for a significant fraction of a chip's overall energy dissipation. Recent research advocates using "resizable" caches to exploit cache requir...
Se-Hyun Yang, Michael D. Powell, Babak Falsafi, T....