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31
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DAC
2006
ACM
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Computer Architecture
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DAC 2006
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Statistical logic cell delay analysis using a current-based model
14 years 11 months ago
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homepages.cae.wisc.edu
A statistical model for the purpose of logic cell timing analysis in the presence of process variations is presented. A new current-based cell delay model is utilized, which can a...
Hanif Fatemi, Shahin Nazarian, Massoud Pedram
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