Statistical logic cell delay analysis using a current-based model

A statistical model for the purpose of logic cell timing analysis in the presence of process variations is presented. A new current-based cell delay model is utilized, which can accurately compute the output waveform for input waveforms of arbitrary shapes subjected to noise. The cell parasitic capacitances are pre-characterized by lookup tables to improve the accuracy. To capture the effect of process parameter variations on the cell behavior, the output voltage waveform of logic cells is modeled by a stochastic Markovian process in which the voltage value probability distribution at each time instance is computed from that of the previous time instance. Next the probability distribution of %Vdd crossing time, i.e., the hitting time of the output voltage stochastic process is computed. Experimental results demonstrate the high accuracy of our cell delay model compared to Monte-Carlo-based SPICE simulations. Categories and Subject Descriptors: B.8.2 [Performance and Reliability]: Perf...

• Type: Conference
• Year: 2006
• Where: DAC
• Authors: Hanif Fatemi, Shahin Nazarian, Massoud Pedram
• Keywords: Cell Delay Model, DAC 2006, Design Automation, Output Voltage Waveform, Voltage Stochastic Process