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DFT
2009
IEEE
139views VLSI» more  DFT 2009»
14 years 3 months ago
Reduced Precision Checking for a Floating Point Adder
We present an error detection technique for a floating point adder which uses a checker adder of reduced precision to determine if the result is correct within some error bound. O...
Patrick J. Eibl, Andrew D. Cook, Daniel J. Sorin