Reduced Precision Checking for a Floating Point Adder

We present an error detection technique for a floating point adder which uses a checker adder of reduced precision to determine if the result is correct within some error bound. Our analysis establishes a relationship between the width of the checker adder’s mantissa and the worst-case magnitude of an undetected error in the primary adder’s result. This relationship allows for a tradeoff between error detection capability and area overhead that is not offered by any previously developed floating point adder checking schemes. Experimental results of fault injection experiments are presented which support our analysis.

• Type: Conference
• Year: 2009
• Where: DFT
• Authors: Patrick J. Eibl, Andrew D. Cook, Daniel J. Sorin
• Keywords: Checker Adder, Checker Adder Mantissa, DFT 2009, Floating Point Adder, VLSI