VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
We describe a new algorithm for floorplan evaluation using timing-driven buffered routing according to a prescribed buffer site map. Specifically, we describe a provably good mult...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
This paper shows that software pipelining can be an effective technique for code generation for coarse-grained reconfigurable instruction set processors. The paper describes a tec...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
In this paper, we explore the concept of using analytical models to efficiently generate delay change curves (DCCs) that can then be used to characterize the impact of noise on an...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
The paper presents two new approaches to multiobjective design space exploration for parametric VLSI systems. Both considerably reduce the number of simulations needed to determin...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
Switching activity estimation is a crucial step in estimating dynamic power consumption in CMOS circuits. In [1], we proposed a new switching probability model based on Bayesian N...
VLSID
2003
IEEE
14 years 7 months ago
2003
IEEE
VLSID
2003
IEEE
14 years 7 months ago
2003
IEEE
The working-zone encoding (WZE) method employing locality of memory reference was previously proposed to reduce address bus switching activity. This paper presents an encoding met...
VLSID
2003
IEEE
14 years 7 months ago
2003
IEEE
Exploitation of silicon capacity will require improvements in design productivity and more scalable system paradigms. Asynchronous message passing networks on chip (NOC) have been...
VLSID
2003
IEEE
14 years 7 months ago
2003
IEEE
Design of efficient System-on-Chips (SoCs) require thorough application analysis to identify various compute intensive parts. These compute intensive parts can be mapped to hardwa...
VLSID
2003
IEEE
2003
IEEE
High Level Modeling and Validation Methodologies for Embedded Systems: Bridging the Productivity Gap
14 years 7 months ago
