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PATMOS
2004
Springer
14 years 5 months ago
Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell
A full-adder implemented by combining branch-based logic and pass-gate logic is presented in this contribution. A comparison between this proposed full-adder (named BBL PT) and its...
Ilham Hassoune, Amaury Nève, Jean-Didier Le...