CSREAESA 2007 | Sciweavers

Transport triggered architecture (TTA) has been shown to provide an efficient way to design application specific instruction set processors. However, the interconnection network of...

Xue-mi Zhao, Zhiying Wang

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CSREAESA
2006

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A Dual-core Embedded System-on-Chip Architecture for Multimedia Signal Processing Applications

14 years 1 months ago

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- This paper presents a dual-core embedded System-on-Chip for a wide range of application fields with particularly high processing demands, including general signal processing, vid...

Hong Yue, Kui Dai, Zhiying Wang

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CSREAESA
2006

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Adaptive Dynamic Voltage Scaling for Real-Time Systems

14 years 1 months ago

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Kiyofumi Tanaka, Akira Imai

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CSREAESA
2006

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The Satellite Data Model

14 years 1 months ago

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The Satellite Data Model (SDM) is part of the Air Force Research Laboratory (AFRL) Responsive Space Testbed Initiative. It is a developing standard for rapid integration of hardwa...

Kenneth Sundberg, Scott Cannon, Todd Hospodarsky, ...

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2006

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Layered Architecture Revised

14 years 1 months ago

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- A systematic approach to building layered software architecture is proposed. Separate layering models required oper abstracting of hardware, persistent data, and communication pr...

Asher Sterkin

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CSREAESA
2006

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In-House Built Bipedal Walking Robot

14 years 1 months ago

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In this project, an in-house built bipedal walking Robot uses two direct current gear motors to power its legs. Each leg could bend at the knee to assist the walking routines. In ...

Kok-Swee Sim, Yee Kin Lum, Chih Ping Tso

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CSREAESA
2006

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Static Program Partitioning for Embedded Processors

14 years 1 months ago

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Modern processors have a small on-chip local memory for instructions. Usually it is in the form of a cache but in some cases it is an addressable memory. In the latter, the user is...

Bageshri Sathe, Uday P. Khedker

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CSREAESA
2006

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Towards a CLI Assembly Format for Embedded Systems

14 years 1 months ago