Sciweavers

DAC
2002
ACM
15 years 15 days ago
An integer linear programming based approach for parallelizing applications in On-chip multiprocessors
With energy consumption becoming one of the first-class optimization parameters in computer system design, compilation techniques that consider performance and energy simultaneous...
Ismail Kadayif, Mahmut T. Kandemir, Ugur Sezer
DAC
2002
ACM
15 years 15 days ago
An energy saving strategy based on adaptive loop parallelization
In this paper, we evaluate an adaptive loop parallelization strategy (i.e., a strategy that allows each loop nest to execute using different number of processors if doing so is be...
Ismail Kadayif, Mahmut T. Kandemir, Mustafa Karak&...
DAC
2002
ACM
15 years 15 days ago
Energy exploration and reduction of SDRAM memory systems
Yongsoo Joo, Yongseok Choi, Hojun Shim, Hyung Gyu ...
DAC
2002
ACM
15 years 15 days ago
Software synthesis from synchronous specifications using logic simulation techniques
This paper addresses the problem of automatic generation of implementation software from high-level functional specifications in the context of embedded system on chip designs. So...
Yunjian Jiang, Robert K. Brayton
DAC
2002
ACM
15 years 15 days ago
Transformation rules for designing CNOT-based quantum circuits
This paper gives a simple but nontrivial set of local transformation rules for Control-NOT(CNOT)-based combinatorial circuits. It is shown that this rule set is complete, namely, ...
Kazuo Iwama, Yahiko Kambayashi, Shigeru Yamashita
DAC
2002
ACM
15 years 15 days ago
Few electron devices: towards hybrid CMOS-SET integrated circuits
Adrian M. Ionescu, Michel J. Declercq, Santanu Mah...
DAC
2002
ACM
15 years 15 days ago
Exploiting operation level parallelism through dynamically reconfigurable datapaths
Increasing non-recurring engineering (NRE) and mask costs are making it harder to turn to hardwired Application Specific Integrated Circuit (ASIC) solutions for high performance a...
Zhining Huang, Sharad Malik
DAC
2002
ACM
15 years 15 days ago
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet pr...
Edson L. Horta, John W. Lockwood, David E. Taylor,...
DAC
2002
ACM
15 years 15 days ago
Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver
We propose Satisfiability Checking (SAT) techniques that lead to a consistent performance improvement of up to 3x over state-ofthe-art SAT solvers like Chaff on important problem ...
Malay K. Ganai, Pranav Ashar, Aarti Gupta, Lintao ...