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    ICCAD
    2005
    IEEE
    130views Hardware» more  ICCAD 2005»
    A cache-defect-aware code placement algorithm for improving the performance of processors
    14 years 8 months ago
    A cache-defect-aware code placement algorithm for improving the performance of processors
    Download  qir.kyushu-u.ac.jp
    — Yield improvement through exploiting fault-free sections of defective chips is a well-known technique [1][2]. The idea is to partition the circuitry of a chip in a way that fau...
    Tohru Ishihara, Farzan Fallah
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