Interconnect-driven optimization is an increasingly important step in high-performance design. Algorithms for buffer insertion have been successfully utilized to reduce delay in gl...
Charles J. Alpert, Anirudh Devgan, Stephen T. Quay
This paper addresses the issue of timing driven gate duplication for delay optimization. Gate duplication has been used extensively for cutset minimization but the usefulness in m...
— Cooperative relaying has recently been recognized as an alternative to MIMO in a typical multi cellular environment. Inserting random delays at the non-regenerative fixed rela...
S. Ben Slimane, Xuesong Li, Bo Zhou, Nauroze Syed,...