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    DAC
    2008
    ACM
    129views Computer Architecture» more  DAC 2008»
    Low power passive equalizer optimization using tritonic step response
    14 years 9 months ago
    Low power passive equalizer optimization using tritonic step response
    Download  learn.tsinghua.edu.cn
    A low power passive equalizer using RL terminator is proposed and optimized in this work. The equalizer includes an inductor in series with the resistive terminator, which boosts ...
    Ling Zhang, Wenjian Yu, Haikun Zhu, Alina Deutsch,...
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    DAC
    2008
    ACM
    110views Computer Architecture» more  DAC 2008»
    Automated hardware-independent scenario identification
    14 years 9 months ago
    Automated hardware-independent scenario identification
    Download  users.elis.ugent.be
    Scenario-based design exploits the time-varying execution behavior of applications by dynamically adapting the system on which they run. This is a particularly interesting design ...
    Juan Hamers, Lieven Eeckhout
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    DAC
    2008
    ACM
    120views Computer Architecture» more  DAC 2008»
    Temperature management in multiprocessor SoCs using online learning
    14 years 9 months ago
    Temperature management in multiprocessor SoCs using online learning
    Download  cseweb.ucsd.edu
    In deep submicron circuits, thermal hot spots and high temperature gradients increase the cooling costs, and degrade reliability and performance. In this paper, we propose a low-co...
    Ayse Kivilcim Coskun, Tajana Simunic Rosing, Kenny...
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    DAC
    2008
    ACM
    145views Computer Architecture» more  DAC 2008»
    Enhancing timing-driven FPGA placement for pipelined netlists
    14 years 9 months ago
    Enhancing timing-driven FPGA placement for pipelined netlists
    Download  www.ee.washington.edu
    FPGA application developers often attempt to use pipelining, Cslowing and retiming to improve the performance of their designs. Unfortunately, such registered netlists present a f...
    Kenneth Eguro, Scott Hauck
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    DAC
    2008
    ACM
    186views Computer Architecture» more  DAC 2008»
    An 8x8 run-time reconfigurable FPGA embedded in a SoC
    14 years 9 months ago
    An 8x8 run-time reconfigurable FPGA embedded in a SoC
    Download  www.tsi.enst.fr
    This paper presents a RTR FPGA embedded in a System on Chip fabricated in 130nm CMOS process. Various aspects of the design flow, from automation to floor-planning are discussed. ...
    Sumanta Chaudhuri, Sylvain Guilley, Florent Flamen...
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    DAC
    2008
    ACM
    182views Computer Architecture» more  DAC 2008»
    Study of the effects of MBUs on the reliability of a 150 nm SRAM device
    14 years 9 months ago
    Study of the effects of MBUs on the reliability of a 150 nm SRAM device
    Download  www.nebrija.es
    1 Soft errors induced by radiation are an increasing problem in the microelectronic field. Although traditional models estimate the reliability of memories suffering Single Event U...
    Juan Antonio Maestro, Pedro Reviriego
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    DAC
    2008
    ACM
    146views Computer Architecture» more  DAC 2008»
    The synthesis of robust polynomial arithmetic with stochastic logic
    14 years 9 months ago
    The synthesis of robust polynomial arithmetic with stochastic logic
    Download  cctbio.ece.umn.edu
    As integrated circuit technology plumbs ever greater depths in the scaling of feature sizes, maintaining the paradigm of deterministic Boolean computation is increasingly challeng...
    Weikang Qian, Marc D. Riedel
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    DAC
    2008
    ACM
    120views Computer Architecture» more  DAC 2008»
    Stochastic integral equation solver for efficient variation-aware interconnect extraction
    14 years 9 months ago
    Stochastic integral equation solver for efficient variation-aware interconnect extraction
    Download  www.mit.edu
    In this paper we present an efficient algorithm for extracting the complete statistical distribution of the input impedance of interconnect structures in the presence of a large n...
    Tarek Moselhy, Luca Daniel
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    DAC
    2008
    ACM
    140views Computer Architecture» more  DAC 2008»
    Transistor level gate modeling for accurate and fast timing, noise, and power analysis
    14 years 9 months ago
    Transistor level gate modeling for accurate and fast timing, noise, and power analysis
    Download  www.clkda.com
    Current source based cell models are becoming a necessity for accurate timing and noise analysis at 65nm and below. Voltage waveform shapes are increasingly more difficult to repr...
    S. Raja, F. Varadi, Murat R. Becer, Joao Geada
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    DAC
    2008
    ACM
    136views Computer Architecture» more  DAC 2008»
    Tunneling and slicing: towards scalable BMC
    14 years 9 months ago
    Tunneling and slicing: towards scalable BMC
    Download  www.nec-labs.com
    Malay K. Ganai, Aarti Gupta
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