DAC
2004
ACM
14 years 4 months ago
2004
ACM
A processor core, previously implemented in a 0.25m Al process, is redesigned for a 0.13m Cu process to create a dualcore processor with 1MB integrated L2 cache, offering an effic...
SBCCI
2006
ACM
14 years 6 months ago
2006
ACM
This paper presents the design of asynchronous circuits on synchronous FPGAs and CPLDs. Different design styles have been investigated through the implementation of dual-rail full...