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    DFT
    1993
    IEEE
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    Layout Level Design for Testability Strategy Applied to a CMOS Cell Library
    13 years 11 months ago
    Layout Level Design for Testability Strategy Applied to a CMOS Cell Library
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    M. Rullán, F. C. Blom, J. Oliver, C. Ferrer
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    DFT
    1993
    IEEE
    90views VLSI» more  DFT 1993»
    High Level Synthesis Techniques for Efficient Built-In-Self Repair
    13 years 11 months ago
    High Level Synthesis Techniques for Efficient Built-In-Self Repair
    Download  www.cs.ucla.edu
    Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey
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    DFT
    1993
    IEEE
    93views VLSI» more  DFT 1993»
    Neural Networks for Multiple Fault Diagnosis in Analog Circuits
    13 years 11 months ago
    Neural Networks for Multiple Fault Diagnosis in Analog Circuits
    Download  bode.diee.unica.it
    Alessandra Fanni, Alessandro Giua, Enrico Sandoli
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