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23

DFT
1993
IEEE

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Layout Level Design for Testability Strategy Applied to a CMOS Cell Library

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Layout Level Design for Testability Strategy Applied to a CMOS Cell Library

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M. Rullán, F. C. Blom, J. Oliver, C. Ferrer

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DFT 1993 | VLSI |

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Added	08 Aug 2010
Updated	08 Aug 2010
Type	Conference
Year	1993
Where	DFT
Authors	M. Rullán, F. C. Blom, J. Oliver, C. Ferrer

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