Cache design for high performance computing requires the realization of two seemingly disjoint goals of higher hit ratios at reduced access times. Recent research advocates the us...
This paper suggests tools that provide significant improvements in the design and verification of FPGAbased digital circuits. These tools include reusable specifications of hardwa...
Valery Sklyarov, Iouliia Skliarova, Pedro Almeida,...
Increasing link speeds have placed enormous burden on the processing requirements and the processors are expected to carry out a variety of tasks. Network Processors (NP) [1] [2] ...
With shrinking feature size of silicon fabrication technology, architects are putting more and more logic into a single die. While one might opt to use these transistors for build...
Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemi...
Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports high degree of reusability and is scalable. In this paper we describe an efficient t...
This paper presents a method with an evolutionary approach to some of the tasks of integrated-circuit (IC) design. The work is focused on application-specific integrated circuits ...
Heuristic algorithms for coloring the edges of large undirected single-edge graphs with (or very close to) the minimal number of colors are presented. Compared to simulated anneal...
Mario Hilgemeier, Nicole Drechsler, Rolf Drechsler
This paper proposes a methodology and a basic structure for the design of wrappers used to adapt cores for use as bus masters. The AMBA AHB protocol is used as a case study in thi...