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    MICRO
    2009
    IEEE
    159views Hardware» more  MICRO 2009»
    Adaptive line placement with the set balancing cache
    14 years 6 months ago
    Adaptive line placement with the set balancing cache
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    Efficient memory hierarchy design is critical due to the increasing gap between the speed of the processors and the memory. One of the sources of inefficiency in current caches is...
    Dyer Rolán, Basilio B. Fraguela, Ramon Doal...
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