Sciweavers

ERSA
2006
86views Hardware» more  ERSA 2006»
14 years 1 months ago
GifT: A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs
In reconfigurable systems, reconfiguration latency has a significant impact on the system performance. In this work, a temporal partitioning algorithm is presented to partition da...
Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedi...
ERSA
2006
133views Hardware» more  ERSA 2006»
14 years 1 months ago
An FPGA based Co-Design Architecture for MIMO Lattice Decoders
MIMO systems have attracted great attentions because of their huge capacity. The hardware implementation of MIMO decoder becomes a challenging task as the complexity of the MIMO sy...
Cao Liang, Jing Ma, Xin-Ming Huang
ERSA
2006
132views Hardware» more  ERSA 2006»
14 years 1 months ago
Combinatorial Optimization in Mapping Generalized Template Matching onto Reconfigurable Computers
: A brief review of mapping generalized template matching operations onto reconfigurable computers is given. A combinatorial optimization process, where the objective is to minimiz...
Xuejun Liang, Qutaibah M. Malluhi
ERSA
2006
82views Hardware» more  ERSA 2006»
14 years 1 months ago
Cache Architectures for Reconfigurable Hardware
The architecture and use of caches for two-level reconfigurable hardware is studied in this paper. The considered two-level reconfigurable hardware performs ordinary reconfiguratio...
Sebastian Lange, Martin Middendorf
ERSA
2006
100views Hardware» more  ERSA 2006»
14 years 1 months ago
Relocation and Defragmentation for Heterogeneous Reconfigurable Systems
Current FPGAs are heterogeneous partially reconfigurable architectures, consisting of several resource types, e. g., logic cells and embedded memory. By using partial reconfigurat...
Markus Koester, Heiko Kalte, Mario Porrmann
ERSA
2006
147views Hardware» more  ERSA 2006»
14 years 1 months ago
Code Partitioning for Reconfigurable High-Performance Computing: A Case Study
In this case study, various ways to partition a code between the microprocessor and FPGA are examined. Discrete image convolution operation with separable kernel is used as the ca...
Volodymyr V. Kindratenko
ERSA
2006
99views Hardware» more  ERSA 2006»
14 years 1 months ago
Low Power Programmable FIR Filtering IP Cores Targeting System-on-a-Reprogrammable-Chip (SoRC)
- This paper presents the design and implementation methodology of some low power programmable FIR filtering IP cores targeting SoRC and compares their performance in term of area,...
Muhammad Akhtar Khan, Abdul Hameed, Ahmet T. Erdog...
ERSA
2006
115views Hardware» more  ERSA 2006»
14 years 1 months ago
Reconfigurable Acceleration of Robust Frequency-Domain Echo Cancellation
Acoustic echo control is of vital interest for hands-free operation of telecommunications equipment. An important property of an acoustic echo controller is its capability to hand...
Chun Hok Ho, Ka Fai Cedric Yiu, Jiaquan Huo, Sven ...
ERSA
2006
129views Hardware» more  ERSA 2006»
14 years 1 months ago
Group-Alignment based Accurate Floating-Point Summation on FPGAs
Floating-point summation is one of the most important operations in scientific/numerical computing applications and also a basic subroutine (SUM) in BLAS (Basic Linear Algebra Sub...
Chuan He, Guan Qin, Mi Lu, Wei Zhao