ERSA
2006
14 years 7 days ago
2006
Reconfigurable supercomputing (RSC) combines programmable logic chips with high performance microprocessors, all communicating over a high bandwidth, low latency interconnection n...
ERSA
2006
14 years 7 days ago
2006
We propose an improved implementation of the SHA-2 hash family to include a multi-mode of operation with minimal latency and hardware requirements over the entire operator. The mul...
ERSA
2006
14 years 7 days ago
2006
This paper deals with the question of task communication and configuration dynamic management in the context of hardware and software implementations. Our approach is based on a c...
ERSA
2006
14 years 7 days ago
2006
Reconfigurable devices, such as FPGAs, introduce into the design workflow of embedded systems a new degree of freedom: the designer can have the system autonomously modify the fun...
ERSA
2006
14 years 7 days ago
2006
Abstract-- In this work the problem of modeling reconfigurable systems behavior with a precise, executable semantics is considered. The possibility of synthesising such models onto...
ERSA
2006
14 years 7 days ago
2006
In this paper we first outline and discuss the issues of currently accepted computational models for hybrid CPU/FPGA systems. Then, we discuss the need for researchers to develop ...
ERSA
2006
14 years 7 days ago
2006
- An intrinsic embedded online evolution system has been designed using Block-based neural networks and implemented on Xilinx VirtexIIPro FPGAs. The designed network can dynamicall...
ERSA
2006
14 years 7 days ago
2006
Abstract-- In heterogeneous tiled System-on-Chip architectures a Network-on-Chip is used to transport messages between processing elements. A reconfigurable network interface is us...
ERSA
2006
14 years 7 days ago
2006
In a coarse-grained reconfigurable architecture, the functions of resources such as Arithmetic Logic Units (ALUs) can be reconfigured. Unlike the programmability of a general purp...
ERSA
2006
14 years 7 days ago
2006
Optically Reconfigurable Gate Arrays (ORGAs), by exploiting the large storage capacity of holographic memory, offer the possibility of providing a virtual gate count that is much l...