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    EURODAC
    1995
    IEEE
    126views VHDL» more  EURODAC 1995»
    Timing optimization by bit-level arithmetic transformations
    14 years 2 months ago
    Timing optimization by bit-level arithmetic transformations
    Download  www.cecs.uci.edu
    This paper describes a method to optimize the performance of data paths. It is based on bit-level arithmetic transformations, and is especially suited to optimize large adder stru...
    Luc Rijnders, Zohair Sahraoui, Paul Six, Hugo De M...
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    EURODAC
    1995
    IEEE
    142views VHDL» more  EURODAC 1995»
    Prediction of radiated electromagnetic emissions from PCB traces based on green dyadics
    14 years 2 months ago
    Prediction of radiated electromagnetic emissions from PCB traces based on green dyadics
    Download  www.cs.york.ac.uk
    Because it costs to solve ElectroMagnetic Compatibility (EMC) problems late in the development process, new methods have to predict radiated electromagnetic emissions at the desig...
    E. Leroux, Flavio G. Canavero, G. Vecchi
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    EURODAC
    1995
    IEEE
    112views VHDL» more  EURODAC 1995»
    On implementation choices for iterative improvement partitioning algorithms
    14 years 2 months ago
    On implementation choices for iterative improvement partitioning algorithms
    Download  vlsicad.ucsd.edu
    Iterative improvement partitioning algorithms such as the FM algorithm of Fiduccia and Mattheyses 8 , the algorithm of Krishnamurthy 13 , and Sanchis's extensions of these al...
    Lars W. Hagen, Dennis J.-H. Huang, Andrew B. Kahng
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    EURODAC
    1995
    IEEE
    293views VHDL» more  EURODAC 1995»
    Functional-level analog macromodeling with piecewise linear signals
    14 years 2 months ago
    Functional-level analog macromodeling with piecewise linear signals
    Download  www.cs.york.ac.uk
    Jerzy Dabrowski
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    EURODAC
    1995
    IEEE
    314views VHDL» more  EURODAC 1995»
    Procedure exlining: a new system-level specification transformation
    14 years 2 months ago
    Procedure exlining: a new system-level specification transformation
    Download  www.cs.ucr.edu
    Frank Vahid
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    EURODAC
    1995
    IEEE
    126views VHDL» more  EURODAC 1995»
    Use of embedded scheduling to compile VHDL for effective parallel simulation
    14 years 2 months ago
    Use of embedded scheduling to compile VHDL for effective parallel simulation
    Download  www.cs.york.ac.uk
    This paper describes VHDL compilation techniques, embodied in the Auriga compiler [3,14], which facilitate parallel or distributed simulation by embedding evaluation scheduling in...
    John Willis, Zhiyuan Li, Tsang-Puu Lin
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    EURODAC
    1995
    IEEE
    152views VHDL» more  EURODAC 1995»
    Information model of a compound graph representation for system and architecture level design
    14 years 2 months ago
    Information model of a compound graph representation for system and architecture level design
    Download  www.cecs.uci.edu
    In order to extract a suitable common core information model, design representations on both system and architecture levels are analyzed. Following the specification trajectory, ...
    Peter Conradi
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    EURODAC
    1995
    IEEE
    138views VHDL» more  EURODAC 1995»
    Reduced design time by load distribution with CAD framework methodology information
    14 years 2 months ago
    Reduced design time by load distribution with CAD framework methodology information
    Download  www.cs.york.ac.uk
    This paper is focused on reducing the design time in a CAD framework environment by the optimal use of resources. A user-transparent load distribution system (Framework based LOad...
    Jürgen Schubert, Arno Kunzmann, Wolfgang Rose...
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    EURODAC
    1995
    IEEE
    202views VHDL» more  EURODAC 1995»
    Hardware-software co-synthesis of fault-tolerant real-time distributed embedded systems
    14 years 2 months ago
    Hardware-software co-synthesis of fault-tolerant real-time distributed embedded systems
    Download  www.cs.york.ac.uk
    Distributed systems are becoming a popular way of implementing many embedded computing applications, automotive control being a common and important example. Such embedded systems...
    Santhanam Srinivasan, Niraj K. Jha
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    EURODAC
    1995
    IEEE
    127views VHDL» more  EURODAC 1995»
    Layout synthesis for datapath designs
    14 years 2 months ago
    Layout synthesis for datapath designs
    Download  www.cs.york.ac.uk
    DPLAYOUT is a layout synthesis tool for bit-sliced datapath designs targeting standard-cell libraries. We developed fast and efficient heuristics for placing the cells in a bit-s...
    Naveen Buddi, Malgorzata Chrzanowska-Jeske, Charle...
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